In recent years, large LED display devices have enjoyed great popularity in concert halls, stadiums, public squares, and other locations.
LED display devices usually have hundreds of thousands of LEDs to display the various pixels making up the various images, LED drive ICs (hereinafter referred to as LED drivers) for driving said LEDs, and controllers for controlling the LED drivers corresponding to the gradation information of the pixels. Said LEDs are driven with pulse currents supplied from said LED driver. For example, they are driven to be on/off for about 200 cycles/sec. Because the on/off period is very short, the luminance of the LED appear continuous to human eye due to the image persistence phenomenon of human vision. The luminance of the LED, that is, the luminance of the pixel can be set stepwise as the pulse width of the pulse current is changed corresponding to the gray level information. For example, the pulse width of the pulse current can be adjusted in 256 steps corresponding the 8-bit gray level information.
Generally speaking, there are two types of LED drivers: the single-grayscale type and the PWM grayscale control type. With the single-grayscale type of LED driver, the 1-bit information that controls LED on/off is received one by one from the controller in the operation. On the other hand, with the PWM grayscale control type of LED driver, the gradation information is received from the controller, and a pulse signal having a pulse width corresponding to the gradation information is generated in the driver.
(Single-grayscale Type LED Driver)
FIG. 17 is a block diagram illustrating a portion of the constitution of an example of the LED display device using a single-grayscale type LED driver. It shows the constitution of the pixels of one line of the overall image.
The LED display device shown in FIG. 17 has 640 LEDs corresponding to 640 pixels per line, LED drivers IC0–IC39 with 16 output channels for driving said LEDs, and controller CT1.
LED drivers IC0–IC39 have input terminals and output terminals for on/off control signals of LED supplied as a bit string from controller CT1, and they are connected in cascade via said input terminals and output terminals. The on/off control signal supplied from controller CT1 to LED driver IC0 of the initial stage is shifted in the order of LED drivers IC1, IC2, . . . synchronously with the common clock signal CLK, and it is finally transferred to last LED driver IC39.
LED drivers IC0–IC39 each have 16-bit shift register REG1, 16-bit latch circuit LAT1, and constant-current driver DRV1 with 16 output channels.
Shift register REG1 sequentially shifts the on/off control signal output as a bit string from the previous-stage LED driver synchronously with clock signal CLK and outputs it to the next-stage LED driver.
Synchronously with latch signal S_LAT commonly supplied from controller CT1 to LED drivers IC0–IC39, latch circuit LAT1 holds the 16-bit on/off control signal held in shift register REG1 and outputs it to constant-current driver DRV.
Constant-current driver DRV1 controls the output currents of output terminals OUT0–OUT15 connected to LED corresponding to the 16-bit on/off control signal held in latch circuit LAT1. That is, there is a one-to-one correspondence between the 16-bit on/off control signal and output terminals OUT0–OUT15. When the bit value is “1,” a constant current is output from the corresponding output terminal, so that the LED is turned on. On the other hand, when the bit value is “0,” the output current from the corresponding output terminal is blocked, so that the LED is turned off. Also, a constant-current output is not a necessity for driver DRV1. It is only necessary for the output current to turn on the LED.
FIG. 18 is a diagram illustrating the bit values of the on/off control signals set corresponding to the output terminals (OUT0–OUT15) of LED drivers IC0–IC39, and the current waveforms for the current flow of the various output terminals to LEDs.
640 LEDs are set to turn on/off simultaneously with latch signal S_LAT fed from controller CT1. With each on/off setting, the 16-bit on/off control signals are applied to shift register REG1 of LED drivers IC0–IC39, respectively. Consequently, clock signal CLK should have a frequency 640 times that of latch signal S_LA.
The frequency of latch signal S_LAT is determined corresponding to the refresh rate and number of gray levels of the image.
For example, when 200 images per second are to be displayed, the frequency of the pulse current output from the LED driver is 200 Hz. If the gray scale is 256, the LEDs are turned on/off for each of the 256 divisions of each period of the 200-Hz pulse current. Consequently, the frequency of latch signal S_LAT becomes about 51 kHz (200 Hz×256).
In the LED display device, in order to reduce the number of the LED drivers in use, plural LEDs are usually connected to 1 output terminal of the LED driver. Usually, the constitution is used in which the LEDs are turned on in a time division scheme.
In this case, the duty ratio (the ratio of the output period of the drive current to 1 pulse period) of the pulse current fed to each LED is limited corresponding to the number of time divisions. For example, if 4 LEDs are driven in the time division scheme (4 time divisions), the duty ratio of the pulse current fed to each LED is limited to 25% or less.
In the period of display of 1 image, pulses in the number of the time division are output. Consequently, if the number of time divisions is 4, compared to the case when the number of time divisions is 1, the frequency of the pulse current output from the LED driver become 4 times higher. Like the aforementioned example, if the refresh rate is 200 and the gray scale is 256, the frequency of the pulse current becomes 800 Hz (200 Hz×4), and the frequency of latch signal S_LAT becomes about 205 kHz (200 Hz×4×256).
Consequently, when the refresh rate is 200, the gray scale is 256, and number of time divisions is 4, frequency fmax1 of clock signal CLK required for transfer of on/off control signal to the LED display device shown in FIG. 16 is given by the following equation.[Mathematical Formula 1]                                                                        f                ⁢                                                                  ⁢                max                ⁢                                                                  ⁢                1                            =                            ⁢                                                200                  ⁡                                      [                                          r                      .                      r                      .                                        ]                                                  ×                                  4                  ⁡                                      [                    duty                    ]                                                  ×                                  256                  ⁡                                      [                    GS                    ]                                                  ×                                  640                  ⁡                                      [                    pixel                    ]                                                                                                                          =                            ⁢                                                200                  ⁡                                      [                                          r                      .                      r                                        ]                                                  ×                                  4                  ⁡                                      [                    duty                    ]                                                  ×                                  256                  ⁡                                      [                    GS                    ]                                                  ×                                  40                  ⁡                                      [                    IC                    ]                                                  ×                                  16                  ⁡                                      [                    output                    ]                                                                                                                          =                            ⁢                              131                ⁡                                  [                  MHz                  ]                                                                                        (        1        )            
In Equation 1, [r.r.] stands for the refresh rate; [duty] refers to the number of time divisions; [pixel] refers to the number of pixels; [GS] refers to the gray scale; [IC] refers to the number of LED drivers; and [output] refers to the number of output channels in the LED driver.
(PWM Grayscale Control Type LED Driver)
FIG. 19 is a block diagram illustrating a portion of the constitution of an example of the LED display device made up of PWM grayscale control type LED driver. Just as FIG. 17, the constitution corresponds to the pixels for 1 line of the total image.
The LED display device shown in FIG. 19 has 640 LEDs, corresponding to 640 pixels per line, LED drivers IC0A–IC39A with 16 output channels and driving said LEDs, and controller CT1A.
LED drivers IC0A–IC39A have input terminals and output terminals of the pulse width setting signals of LEDs fed as a bit string from controller CT1A, and they are connected in cascade via said input terminals and output terminals.
Said LED drivers IC0A–IC39A each have 128 (8×16)-bit shift register REG2, 128 (8×16)-bit latch circuit LAT2, PWM generator PW1, and constant-current driver DRV1. Here, the same part numbers adopted in FIGS. 17 and 19 represent the same structural elements.
Shift register REG2 sequentially shifts the pulse assignment signals output as bit strings from the previous-stage LED driver sequentially synchronously with clock signal CLK, and outputs the signals to the next-stage LED driver.
Synchronously with latch signal S_LAT commonly fed from controller CT1A to LED drivers, latch circuit LAT2 holds the 128-bit pulse width setting signal held in shift register REG2, and outputs the signal to PWM generator PW1.
From the 128-bit pulse width setting signal held in latch circuit LAT2, PWM generator PW1 receives the 8-bit pulse width setting signals for the 16 output channels, respectively, and it generates 16 pulse signals with the corresponding pulse width.
More specifically, PWM generator PW1 counts grayscale clock signal GSCLK fed commonly from controller CT1A to the LED drivers, compares the count value to the value of the 8-bit pulse width setting signal obtained from latch circuit LAT2, and sets the values of the pulse signals corresponding to the output channels to “1” or “0.” The 8-bit pulse width setting signal has a value in the range of 0–255, and corresponding to the result of comparison of said value to the count value, the timing for inverting the value of the pulse signal, that is, the pulse width, is determined. Consequently, the grayscale value becomes 256. The count value of grayscale clock signal GSCLK is initialized synchronously with reset signal S_RST fed commonly from controller CT1A to the LED drivers.
FIG. 20 is a timing diagram illustrating the timing relationship of the various signals of the LED display device shown in FIG. 19.
In shift register REG2 of LED drivers IC0A–IC39A, 128-bit pulse width setting signals are transferred in each cycle of the pulse current (FIGS. 20(E)–(G)). After completion of the transfer, the transferred pulse width setting signal is held in latch circuit LAT2 synchronously with latch signal S_LAT (FIG. 20(C)). Then, in PWM generator PW1, the count value of grayscale clock signal GSCLK is initialized, and the comparison of the new pulse width setting signal held in latch circuit LAT2 to the count value of grayscale clock signal GSCLK is initiated. The pulse width of the pulse current of the output channels is set corresponding to the comparison result.
Grayscale clock signal GSCLK (FIG. 20(D)) has a period obtained by dividing 1 period of the pulse current fed to LED (FIGS. 20(E)–(G)) by the gray scale.
As in the aforementioned example, if the refresh rate is 200 and number of time divisions is 4, the gray scale is 256, and frequency fmax2a of grayscale clock signal GSCLK can be found by the following equation.[Mathematical Formula 2]                                                                        f                ⁢                                                                  ⁢                max                ⁢                                                                  ⁢                2                ⁢                a                            =                            ⁢                                                200                  ⁡                                      [                                          r                      .                      r                      .                                        ]                                                  ×                                  4                  ⁡                                      [                    duty                    ]                                                  ×                                  256                  ⁡                                      [                    GS                    ]                                                                                                                          =                            ⁢                              205                ⁡                                  [                  kHz                  ]                                                                                        (        2        )            
Also, during 1 cycle of the pulse current, 8-bit pulse width setting signals for 640 pixels are transferred from controller CT1A to LED drivers IC0A–IC39A. Consequently, clock signal CLK should have a frequency (640×8) times that of the pulse current.
As in the aforementioned example, if the refresh rate is 200 and the number of time divisions is 4, frequency fmax2b of clock signal CLK can be found by the following equation.[Mathematical Formula 3]                                                                        f                ⁢                                                                  ⁢                max                ⁢                                                                  ⁢                2                ⁢                b                            =                            ⁢                                                200                  ⁡                                      [                                          r                      .                      r                      .                                        ]                                                  ×                                  4                  ⁡                                      [                    duty                    ]                                                  ×                                  640                  ⁡                                      [                    pixel                    ]                                                  ×                                  8                  ⁡                                      [                    bit                    ]                                                                                                                          =                            ⁢                              4.1                ⁡                                  [                  MHz                  ]                                                                                        (        3        )            
The single-grayscale type LED driver allows for a relatively simple circuit constitution. Thus, the cost can be held down, which is advantageous.
However, each LED should be turned on/off individually. Consequently, a very high communication speed is required between the controller and the LED driver, which is undesirable. For example, with a square display panel measuring several meters per side, it becomes very difficult to transmit the high-frequency signal shown in Equation 1.
There is a method in which the transmission can be performed for a high-frequency signal by increasing the number of controllers and reducing the transmission distance of the signals. For example, in a commonly adopted method, an image with 640 pixels per line is divided into four sections in the horizontal line direction, and a controller is set for each image region with a width of 160 pixels. As a result, the communication distance between controller and LED driver can be reduced. However, since the number of controllers is quadrupled, the cost increases, which is undesirable.
On the other hand, the PWM grayscale control type LED driver requires less data for processing than the single-grayscale type LED driver. Consequently, the communication speed between the controller and the LED driver can be suppressed. For example, transmission of the signals at the frequency shown in Equations 2 and 3 can be performed without increasing the number of controllers.
However, the circuit constitution of the PWM grayscale control type LED driver is more complicated than that of the single-grayscale type LED driver. As a result, the cost increases, which is undesirable.
The purpose of the present invention is to solve the aforementioned problems of the conventional methods by providing a pulse signal generator which can reduce the quantity of information that must be transmitted for setting the pulse width, as well as a display device with a simple constitution utilizing said pulse signal generator.